Modern electronics, such as smart phones, personal digital assistants, location based services devices, digital cameras, music players, servers, and storage arrays, are packing more integrated circuits into an ever shrinking physical space with expectations for decreasing cost. One cornerstone for electronics to continue proliferation into everyday life is the non-volatile storage of information such as cellular phone numbers, digital pictures, or music files. Numerous technologies have been developed to meet these requirements.
As semiconductor technologies shrink the feature size of active components, more function is packed into each integrated device. In order to keep up with the trend of shrinking component size, there is a need for further memory cell size reduction. As the cell size shrinks, there are several issues that need to be addressed. One of them is the short channel effect that degrades the cell performance as the channel length shrinks. Another issue is the reduction in drive current as the channel width shrinks, which also degrades the cell performance.
“Flash” EEPROM, or Flash memory, combines the advantages of the high density and low cost of EPROM with the electrical eraseability of EEPROM. Flash memory can be rewritten electrically and can hold its contents without power. Contemporary Flash memories are designed in a floating gate or a charge trapping architecture. Each architecture has advantages and disadvantages.
The floating gate architecture offers implementation simplicity. This architecture embeds a gate structure, called a floating gate, inside a conventional metal oxide semiconductor (MOS) transistor gate stack. Electrons can be injected and stored in the floating gate as well as erased using an electrical field or ultraviolet light. The stored information may be interpreted as a value “0” or “1” from the threshold voltage value depending upon charge stored in the floating gate. As the demand for Flash memories increases, the Flash memories must scale with new semiconductor processes. However, new semiconductor process causes a reduction of key feature sizes in Flash memories of the floating gate architecture which results in undesired increase in programming time and decrease in data retention.
The charge trapping architecture offers improved scalability to new semiconductor processes compared to the floating gate architecture. One implementation of the charge trapping architecture is a silicon-oxide-nitride-oxide semiconductor (SONOS) where the charge is trapped in the nitride layer. Leakage and charge-trapping efficiency are two major parameters considered in device performance evaluation. Charge-trapping efficiency determines if the memory devices can keep enough charges in the storage nodes after program/erase operation and is reflected in retention characteristics. It is especially critical when the leakage behavior of storage devices is inevitable. SONOS Flash memories suffer from poor programming performance. Silicon content in the nitride layer improves the programming and erasing performances but offers poor data retention. Although silicon content plays an important role in charge-trapping efficiency, it does not have the same constructive effect on leakage characteristics.
A significant amount of research has been undertaken to produce Fin FET technology. The design utilizes a silicon fin protruding from the substrate to form a source/drain structure and a gate structure patterned perpendicular to the source/drain structure. The gate wraps around the fin. This geometry creates a double gate on the Fin FET reducing leakage current when in the off state.
An aspect of the Fin FET is that the gate wraps around the fin like channel, thus it has increased gate control to reduce the short channel effect. The channel length scaling becomes easier. At the same time, the gate wrap-around also increases the actual channel width from the side wall of the fin, without increasing the physical channel width. The Fin FET concept can be applied to both floating gate and nitride based technology. However, due to the ONO interpoly layer and physical size of the floating gate, the cell size scalability advantage of Fin FET for floating gate technology is not as great as it is for nitride based FLASH technology.
Thus, a need still remains for a memory system providing low cost manufacturing, improved yields, improved programming performance, and improved data retention of memory in a memory sub-system. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.
Solutions to these problems have long been sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.